1. Field of the Invention
Generally, the present disclosure relates to microstructures, such as advanced integrated circuits, and, more particularly, to material systems including silicon oxide based dielectrics having a low dielectric constant.
2. Description of the Related Art
In the fabrication of modern microstructures, such as integrated circuits, there is a continuous drive to improve performance in view of operational behavior and diversity of functions integrated in a single microstructure device. For this purpose, there is an ongoing demand to steadily reduce the feature sizes of microstructure elements, thereby enhancing the functionality of these structures. For instance, in modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby increasing performance of these circuits in terms of speed and/or power consumption and/or diversity of functions. As the size of individual circuit elements is reduced with every new circuit generation, thereby improving, for example, the switching speed of the transistor elements, frequently new materials may be required in order to not unduly offset any advantages that may be achieved by reducing the feature sizes of the individual components of microstructure devices, such as circuit elements and the like. For instance, upon shrinking the critical dimensions of transistors, thereby increasing the density of individual circuit elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines are also reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per unit die area as typically two or more interconnections are required for each individual circuit element. Thus, a plurality of stacked “wiring” layers, also referred to as metallization layers, is usually provided, wherein individual metal lines of one metallization layer are connected to individual metal lines of an overlying or underlying metallization layer by so-called vias. Despite the provision of a plurality of metallization layers, reduced dimensions of the interconnect lines are necessary to comply with the enormous complexity of, for instance, modern CPUs, memory chips, ASICs (application specific ICs) and the like.
Advanced integrated circuits, including transistor elements having a critical dimension of 0.05 μm and even less, may, therefore, typically be operated at significantly increased current densities of up to several kA per cm' in the individual interconnect structures, despite the provision of a relatively large number of metallization layers, owing to the increased number of circuit elements per unit area. Consequently, well-established materials, such as aluminum, are being replaced by copper and copper alloys, i.e., materials with a significantly lower electrical resistivity and improved resistance to electromigration even at considerably higher current densities compared to aluminum.
The introduction of copper into the fabrication of microstructures and integrated circuits comes along with a plurality of severe problems residing in copper's characteristics to readily diffuse in silicon dioxide and other dielectric materials, as well as the fact that copper may not be readily patterned on the basis of well-established plasma assisted etch recipes. For example, based on conventional plasma assisted etch processes, copper may not substantially form any volatile etch byproducts such that the patterning of a continuous copper layer with a thickness that is appropriate for forming metal lines may not be compatible with presently available etch strategies. Consequently, the so-called damascene or inlaid process technique may typically be applied in which a dielectric material may be formed first and may be subsequently patterned in order to receive trenches and via openings, which may be subsequently filled with the copper-based material by using, for instance, electrochemical deposition techniques. Moreover, copper has a pronounced diffusivity in a plurality of dielectric materials, such as silicon dioxide based materials, which are frequently used as interlayer dielectric materials, thereby requiring the deposition of appropriate barrier materials prior to actually filling corresponding trenches and via openings with the copper-based material. Although silicon nitride and related materials may have excellent diffusion blocking capabilities, using silicon nitride as an interlayer dielectric material is less than desirable due to the moderately high dielectric constant, which may result in a non-acceptable performance degradation of the metallization system. Similarly, in sophisticated applications, the reduced distance of metal lines may require a new type of dielectric material in order to reduce signal propagation delay, cross-talking and the like, which are typically associated with a moderately high capacitive coupling between neighboring metal lines. For this reason, so-called low-k dielectric materials are increasingly being employed, which may generally have a dielectric constant of 3.0 or less, thereby maintaining the parasitic capacitance values in the metallization system at an acceptable level, even for the overall reduced dimensions in sophisticated applications.
Since silicon dioxide has been widely used in the fabrication of microstructure devices and integrated circuits, a plurality of modified silicon oxide based materials have been developed in recent years in order to provide dielectric materials with a reduced dielectric constant on the basis of precursor materials and process techniques that may be compatible with the overall manufacturing process for microstructure devices and integrated circuits. For instance, silicon oxide materials with a moderately high amount of carbon and hydrogen, for instance referred to as SICOH materials, have become a frequently used low-k dielectric material, which may be formed on the basis of a plurality of precursor materials, such as silane-based materials, in combination with ammonium and the like, which may be applied by chemical vapor deposition (CVD) techniques and the like. In other cases, spin-on glass (SOG) materials may be modified so as to contain a desired high fraction of carbon and hydrogen, thereby providing the desired low dielectric constant.
In still other sophisticated approaches, the dielectric constant of these materials may be even further reduced by further reducing the overall density of these materials, which may be accomplished by incorporating a plurality of cavities of nano dimensions, also referred to as pores, which may represent gas-filled or air-filled cavities, within the dielectric material, thereby obtaining a desired reduced dielectric constant. Although the permittivity of these dielectric materials may be reduced by incorporating carbon and forming a corresponding porous structure, which may result in a very increased surface area at interface regions connecting to other materials, the overall mechanical and chemical characteristics of these low-k and ultra low-k (ULK) materials may also be significantly altered and may result in additional problems during the processing of these materials.
For example, as discussed above, the dielectric material may typically have to be provided first and may be patterned so as to receive trenches and via openings, which may require the exposure of the sensitive low-k dielectric materials to various reactive process atmospheres. That is, the patterning of the dielectric material may typically involve the formation of an etch mask based on a resist material and the like followed by plasma assisted etch processes in order to form the trenches and via openings corresponding to the design rules of the device under consideration. Thereafter, cleaning processes may have to be performed in order to remove contaminants and other etch byproducts prior to depositing materials, such as conductive barrier materials and the like. Consequently, at least certain surface areas of the sensitive low-k dielectric materials may be exposed to plasma assisted processes, such as resist strip processes performed on the basis of an oxygen plasma, wet chemical reagents in the form of acids, aggressive bases, alcohols and the like, which may thus result in a certain degree of surface modification or damage. For instance, the low-k dielectric materials may typically be provided with a hydrophobic surface in order to avoid the incorporation of OH groups and the like, which may represent polarizable groups that may therefore respond to an electrical field, thereby significantly increasing the resulting permittivity of the surface portion of the material. Upon exposure of the hydrophobic surface to reactive atmospheres, such as plasma, aggressive wet chemical reagents and the like, the hydrocarbon groups of the hydrophobic surface area may be replaced by other groups and may finally result in the creation of silanol groups, which result in a significant increase of the dielectric constant at the surface area of the dielectric material. This surface modification or damaging may result in a significant modification of the dielectric behavior of the metallization system which may not be compatible with the performance requirements of sophisticated integrated circuits. Hence, great efforts are being made in providing silicon oxide based low-k dielectric materials while avoiding or at least reducing the surface modification during the patterning of the sensitive dielectric material. To this end, it has been suggested to selectively remove a damaged surface portion of the low-k dielectric materials on the basis of appropriate etch strategies so as to re-establish the desired hydrophobic surface characteristics. In this case, appropriate etch recipes may have to be applied without exposure of the resulting structure to any further aggressive process ambient in order to maintain the hydrophobic nature of the surface until the deposition of a conductive barrier material and the like. Additionally the material removal may result in an increase of the critical dimensions of the metal lines and vias, which may be undesirable in view of enhanced packing density, since the increased critical dimension may have to be taken into consideration when designing the metallization system under consideration.
In other approaches the hydrophobic nature may be re-established by performing a surface treatment after exposing the low-k dielectric material to the aggressive process ambient, which may be accomplished by using specific compounds. For example, U.S. Pat. No. 7,029,826 discloses a surface treatment of porous silica materials by exposing the damaged surface area to one or more compounds having the formula as follows: R3SINHSIR3, RXSICLY, RXCI(OH)Y, R3SIOSIR3, RXSI(OR)Y, MPSI(HO)4-P, RXSI(OCOCH3) YR and combinations thereof, wherein X is an integer ranging from 1-3, Y is an integer ranging from 1-3 such that Y=4−X, P is an integer ranging from 2-3, each R is selected from hydrogen and a hydrophobic organic moiety, each M is an independently selected hydrophobic organic moiety, and R and M can be the same or different.
Although a surface treatment with chemical reagents as specified in this document may provide enhanced hydrophobic surface conditions of nanoporous silica dielectric materials, there is still room for further improvement, for instance with respect to enhancing overall process efficiency and the like.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.